The present invention generally relates to a method and apparatus for generating layout data, and more particularly, to a method and device for generating layout data for optimizing external power supply wirings to function blocks in a semiconductor integrated circuit device.
In a conventional process for determining the external power supply wirings to function blocks for a semiconductor integrated circuit device, an external power network for external power wirings is generated based on information about an internal power network of each function block and information about the current consumption of each power supply terminal of each function block. The external power network includes resistance elements, sampled from the external power wiring pattern and having predetermined resistance values, and current sources connected to nodes of the external power wirings and having predetermined current consumption values. The external power network is analyzed using a matrix expression, for example, and based on the analysis results, the width and the wiring path of the external power wirings connected to the power supply terminals of each function block are determined.
However, if information about the internal power network or information about the current consumption of each power supply terminal of the function block is not included in the function block library data, it is difficult to lay out the external power wiring having an optimum width. Accordingly, if information about the function block is insufficient, it is desirable to obtain the current consumption of each power supply terminal in order to lay out the external power wiring having the optimum width.
Circuit simulations are used to obtain the current consumption. First, resistance elements are sampled from the layout data of the function block based on a gate length, gate width, and the wiring length between the nodes of the internal power wirings, and an equivalent circuit is generated from the sampled resistance elements. Then, the electrical operation simulation of the equivalent circuit is carried out and based on the simulation result, the current consumption in each power supply terminal of the function block is obtained. Further, based on the current consumption, an external power network is generated, and the external power network is analyzed. Then, based on the analysis result, the layout of the external power wirings is determined. This method accurately determines the current consumption. However, the circuit simulation is time-consuming.
Another method involves setting the same current consumption ratio for all of the power supply terminals of the function block. Because this method generates the external power network based on a set current consumption ratio, no circuit simulation is required.
However, the current consumption for the power supply terminals usually varies according to the arrangement position of a transistor as a current source. Accordingly, differences in current consumption are not reflected in the analysis result of the external power network. As a result, the layout of the external power wirings is not optimized.
It is an object of the present invention to provide a method and apparatus for laying out an optimized external power wiring pattern in a short time.